Synplicity Details New Synthesis Methodology for SoC and Programmable SoC Design

New MultiPoint Synthesis Technology Overcomes Hurdles to Designing Large, IP-Intensive ASICs and PLDs

SUNNYVALE, Calif.--(BUSINESS WIRE)--May 13, 2002-- Synplicity, Inc. (Nasdaq:SYNP - News), a leading supplier of software for the design and verification of semiconductors, today introduced its new MultiPoint(TM) synthesis technology targeting multi-million gate system-on-a-chip (SoC) and programmable system-on-a-chip (PSoC) integrated circuits. By providing a high productivity design methodology that is scalable to tens of millions of gates, the new technology addresses design challenges that are emerging as application specific integrated circuits (ASICs) and programmable logic devices (PLDs) become more complex. Synplicity intends to deploy the MultiPoint technology within each of its ASIC and PLD synthesis products, and today announced its Synplify ASIC® software is the first product to support the MultiPoint synthesis flow (see press announcement titled "Synplicity Strengthens Synplify ASIC Software for High-Performance SoC Designs" made today).

"SoC and PSoC designs are pushing the limits of existing synthesis methodologies, the result being that designers must expend a lot of manual effort managing synthesis flows that can result in long runtimes and sub-optimal design quality," said Ken McElvain, chief technology officer, Synplicity. "The MultiPoint technology combines the quality of results and ease-of-use of top-down flows with the stability, fast runtimes, and capacity of a bottom-up flow. By combining the best of existing methodologies with new technology, we believe we are able to deliver an automated high-productivity incremental synthesis solution for large high-performance designs. We also believe the MultiPoint technology is a key milestone in our strategy to deliver the best possible results in the shortest amount of time to both ASIC and FPGA designers."

Synthesis Methodology for Complex Designs

By combining new technology with the best of existing design methodologies, Synplicity"s MultiPoint technology enables a superior methodology for the most critical design flow requirements. Specifically, MultiPoint synthesis provides better quality of timing and area results, faster runtime, the ability to handle very large designs, ease of project setup and constraint entry, and intelligent handling of intellectual property (IP) blocks. The MultiPoint technology employs incremental design techniques that enable parts of a design to remain unchanged while others are synthesized. The technology uniquely creates interface logic models (ILMs) based upon user-defined "compile points," or instructions to the synthesis tool for modeling and synthesizing a particular portion of the design. Unlike other incremental flows where cross-boundary optimizations are difficult, the MultiPoint technology can optimize across design partitions using the same information needed for a top-down synthesis flow, enabling the highest design performance.

To address design team productivity, the MultiPoint technology incorporates a unique difference-based incremental synthesis approach. This approach eliminates the need for re-synthesis that is common with time-stamp-based incremental flows by only re-synthesizing design entities that will have a different gate-level netlist due to code or constraint changes. Products that incorporate the MultiPoint technology also can deliver traditional top-down or bottom-up flows, enabling designers the flexibility to implement the most appropriate flow to meet their design requirements.

The MultiPoint flow also provides a superior solution to integrating IP into a design due to its ability to automatically model the IP and use the timing information for synthesis. For example, with the MultiPoint technology RTL IP that is instantiated into a design can have logic optimized both inside the IP block and in the adjacent modules without impacting port assignments for the IP core. If it is a hard IP block (i.e. gate-level netlist), the MultiPoint technology will automatically model the IP block, thus saving runtime and memory. For designs with replicated logic or IP blocks, the MultiPoint technology allows the designer to control how each unique instance is treated in terms of boundary optimizations, without the runtime penalty of re-synthesizing each instance.

SoC and PSoC Design Challenges Drive New Methodology

For ASIC designers, the MultiPoint technology delivers a methodology for implementing highly complex designs, at a time when deeper submicron processes are driving typical design sizes above a million gates. According to market research firm Collett International, this year most ASIC designs will be implemented in 0.13 micron or 0.18 micron process technology and nearly all will include some form of IP or replicated logic. Existing methodologies -- top-down, bottom-up, or a hybrid of the two -- cannot handle this growing complexity. For example, the traditional bottom-up design flow, or synthesizing lower modules of a design before synthesizing the upper modules, can require many cumbersome scripts and time budgeting, and can inhibit boundary optimization which leads to sub-optimal design performance. Similarly, synthesizing the design hierarchy all at once in a top-down flow is ideal for delivering the best design performance, but is limited by the memory capacity of the computer, as well as long runtimes for synthesizing the entire design.

Likewise, emerging programmable SoC devices include capabilities such as complex I/Os and embedded processors, and offer up to 10 million PLD-gate capacities. With this increase in complexity come design challenges such as meeting timing, longer runtimes and preventing iterations between synthesis and place-and-route. Programmable logic vendors are responding to customer needs with new incremental place and route capabilities. Applying an incremental MultiPoint flow to these designs can significantly improve runtimes for both synthesis and place and route.

For more information on the MultiPoint technology, please visit http://www.synplicity.com.

About Synplicity

Synplicity, Inc. (Nasdaq: SYNP - News) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in networking and communications, computer and peripheral, consumer and military/aerospace electronics systems. Recognizing the company"s industry-leading position, Dataquest named Synplicity as the No. 1 provider of PLD synthesis tools in 2000 with 45 percent market share. Synplicity leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs) and system-on-chip (SoC) integrated circuits. The company"s fast, easy-to-use products offer high quality of results, support industry-standard design languages (VHDL and Verilog) and run on popular platforms. As of March 31, 2002, Synplicity employed 269 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif. For more information on Synplicity, visit http://www.synplicity.com.

The specific features, functionality and release timing of any new terminology as described in this press release remain at the sole discretion of Synplicity, Inc., and Synplicity does not make any warranty as to when or if such specific features, functionality or releases may occur.

Synplicity and Synplify ASIC are registered trademarks of Synplicity, Inc. MultiPoint is a trademark of Synplicity, Inc. All other brands or products are the trademarks or registered trademarks of their respective owners.

     Synplicity, Inc., Sunnyvale
     Reader Contact:
     John Gallagher, 408/215-6000
     johng@synplicity.com
        or
     Porter Novelli
     PR Contact:
     Steve Gabriel, 408/369-1500
     steve.gabriel@porternovelli.com